Hands-On: Tool Qualification Package

% Tool Qualification Level determination for Embedded Coder

% Tool: MathWorks Embedded Coder R2024b
% Intended use: generate ASIL-D compliant C code from MATLAB/Simulink
%               models for ARM Cortex-M7 target

% Step 1: Determine Tool Impact (TI)
% Q: Could a malfunction of Embedded Coder introduce faults
%    into the safety-relevant software without being detected?
% A: YES -- a code generator bug could produce wrong C code
% TI = TI3

% Step 2: Determine Tool Error Detection (TD)
% Detection methods:
% D1: Back-to-back MiL/SiL comparison (catches most gen errors)
% D2: Static analysis (Polyspace) of generated code
% D3: HiL testing of generated code on real ECU
% Assessment: D1+D2+D3 = medium-high confidence => TD2

% Step 3: TCL = f(TI3, TD2) = TCL2
%
% TCL2 requires:
% - Tool qualification report
% - Validation tests for functions used
% - Increased confidence through usage experience
% (MathWorks TQP covers most of this)

fprintf("Tool: Embedded Coder R2024b\n");
fprintf("TI: TI3 (can introduce faults)\n");
fprintf("TD: TD2 (MiL/SiL + static analysis)\n");
fprintf("TCL: TCL2\n");
fprintf("Qualification: Tool qualification report required\n");

% Validation test plan for Embedded Coder (project-specific)
% Focus: functions used in SpeedController ASIL-D model

% TVT-EC-001: Gain block code generation
% Purpose: verify single-precision gain generates correct C code
% Model: Gain block K=10.0, input=single, output=single
% Expected code: y = 10.0F * u;
% Verification: parse generated .c file; compare output

% TVT-EC-002: Discrete integrator code generation
% Purpose: verify Unit Delay generates z^-1 behaviour
% Model: Discrete-Time Integrator Ts=0.01, initial=0
% Expected: accumulates input*Ts each step
% Verification: MiL/SiL comparison; verify identical output

% TVT-EC-003: Saturation block clamps at limits
% Purpose: verify overflow protection generates correct code
% Model: Saturation(-100, 100) on int16 signal
% Expected: clamps at -100 and +100 exactly
% Verification: run above-limit input; check output = limit

% TVT-EC-004: Stateflow state entry action
% Purpose: verify entry action executes exactly once on state entry
% Model: 2-state chart; entry: counter++
% Expected: counter increments exactly once per state entry
% Verification: SiL simulation; count increments

fprintf("Validation test plan: 4 critical functions covered\n");
fprintf("Execute tests and record PASS/FAIL in TQP report\n");