Memory-Mapped I/O & Register Access

#include 

/* Method 1: Direct pointer macro (simple, widely used) */
#define GPIO_DATA    (*(volatile uint32_t *)0xF0001000u)
#define GPIO_DIR     (*(volatile uint32_t *)0xF0001004u)
#define GPIO_OEN     (*(volatile uint32_t *)0xF0001008u)

void gpio_set_output(uint8_t pin, uint8_t value)
{
    GPIO_DIR |=  (1u << pin);     /* set direction to output */
    GPIO_OEN |=  (1u << pin);     /* enable output driver */
    if (value) GPIO_DATA |=  (1u << pin);
    else       GPIO_DATA &= ~(1u << pin);
}

/* Method 2: Base address + offset array (cleaner for many registers) */
typedef volatile uint32_t Reg32_t;
#define CAN0_BASE  0xF0200000u
#define CAN0       ((Reg32_t *)(CAN0_BASE))

#define CAN_MCR_OFFSET   0u   /* byte offset / sizeof(uint32_t) */
#define CAN_SR_OFFSET    1u
#define CAN_BTR_OFFSET   2u

/* CAN0[CAN_MCR_OFFSET] accesses address 0xF0200000 + 0*4 = 0xF0200000 */
CAN0[CAN_MCR_OFFSET] |= (1u << 0u);  /* set INIT bit */

/* Method 3: Struct overlay (most readable; use with caution for padding) */
typedef struct {
    volatile uint32_t MCR;    /* +0x00 */
    volatile uint32_t SR;     /* +0x04 */
    volatile uint32_t BTR;    /* +0x08 */
    volatile uint32_t reserved[29];
    volatile uint32_t IF1CR;  /* +0x80 */
} Can_Regs_t;

Can_Regs_t * const CAN0_REGS = (Can_Regs_t *)CAN0_BASE;

#include 

#define GPIO_DATA  (*(volatile uint32_t *)0xF0001000u)

/* Problem: non-atomic RMW on a shared register */
/* In interrupt context: can corrupt bits set by other code */
void gpio_set_bit_unsafe(uint8_t pin)
{
    GPIO_DATA |= (1u << pin);   /* READ - MODIFY - WRITE: 3 separate operations */
    /* An ISR between any two of these steps corrupts the value */
}

/* Solution 1: Disable interrupts around RMW */
void gpio_set_bit_critical(uint8_t pin)
{
    uint32_t saved = disable_interrupts();   /* save and disable */
    GPIO_DATA |= (1u << pin);
    restore_interrupts(saved);               /* restore previous state */
}

/* Solution 2: Use hardware atomic bit-set/bit-clear registers */
/* Many MCUs provide alias regions that atomically set/clear bits: */
#define GPIO_BITSET  (*(volatile uint32_t *)0xF0001200u)  /* write 1 to set */
#define GPIO_BITCLR  (*(volatile uint32_t *)0xF0001204u)  /* write 1 to clear */

void gpio_set_bit_atomic(uint8_t pin)  { GPIO_BITSET = (1u << pin); }
void gpio_clr_bit_atomic(uint8_t pin)  { GPIO_BITCLR = (1u << pin); }

/* Solution 3: Cortex-M Bit-Banding (if MCU supports it) */
/* Maps each bit to its own 32-bit address in the bit-band alias region */
#define BITBAND_SRAM(addr, bit)      (*(volatile uint32_t *)(0x22000000u + (((uint32_t)(addr)-0x20000000u)*32u) + ((bit)*4u)))

#include 
#include "Std_Types.h"

/* SPI peripheral init sequence — demonstrates ordered register writes */
/* Order matters: configure before enable; wrong order may cause fault */

#define SPI0_BASE   0xF0100000u
typedef struct {
    volatile uint32_t CR1;     /* Control Register 1 */
    volatile uint32_t CR2;     /* Control Register 2 */
    volatile uint32_t SR;      /* Status Register */
    volatile uint32_t DR;      /* Data Register */
} Spi_Regs_t;

#define SPI0  ((Spi_Regs_t *)SPI0_BASE)

/* SPI CR1 bits */
#define SPI_CR1_SPE     (1u << 6u)   /* SPI Enable */
#define SPI_CR1_MSTR    (1u << 2u)   /* Master mode */
#define SPI_CR1_CPOL    (1u << 1u)   /* Clock Polarity */
#define SPI_CR1_CPHA    (1u << 0u)   /* Clock Phase */
#define SPI_CR1_BR_DIV8 (0x2u << 3u) /* Baud rate: fPCLK/8 */

Std_ReturnType Spi_Init(void)
{
    /* Step 1: disable SPI before configuring */
    SPI0->CR1 &= ~SPI_CR1_SPE;

    /* Step 2: configure mode, baud rate, frame format */
    SPI0->CR1 = SPI_CR1_MSTR      /* master mode */
              | SPI_CR1_BR_DIV8   /* clock = PCLK/8 */
              | SPI_CR1_CPOL      /* CPOL=1: idle high */
              | SPI_CR1_CPHA;     /* CPHA=1: sample on trailing edge */

    /* Step 3: configure data size, interrupt enable */
    SPI0->CR2 = (0x07u << 8u);    /* 8-bit data size */

    /* Step 4: enable only after all config complete */
    SPI0->CR1 |= SPI_CR1_SPE;

    /* Step 5: verify: check SR for error flags */
    return ((SPI0->SR & 0x80u) == 0u) ? E_OK : E_NOT_OK;
}