Interrupt Handling & Priority Schemes - Embedded C/C++ for Automotive

ARM Cortex-M NVIC Architecture

Cortex-M NVIC Interrupt Priority Model

  Priority levels: 0 (highest) → 255 (lowest)
  ARM Cortex-M4: 4 bits of priority = 16 levels (0,16,32,...,240)
  Aurix TriCore: priority 0 (lowest) → 255 (highest) — REVERSED from Cortex-M

  ┌─────────────────────────────────────────────────────────────────┐
  │ Pre-emption Priority  │  Sub-Priority                          │
  │ (determines nesting)  │  (tiebreak within same pre-emption)    │
  └─────────────────────────────────────────────────────────────────┘
  Configured by: NVIC_SetPriority(IRQn, priority)
  Read back via: NVIC_GetPriority(IRQn)

  Interrupt flow:
  1. Peripheral sets pending flag → NVIC receives interrupt request
  2. If priority > current running priority: CPU pre-empts current task
  3. Hardware auto-pushes 8 registers onto stack (xPSR, PC, LR, R12, R3-R0)
  4. CPU jumps to ISR via vector table
  5. ISR clears pending flag (usually by reading/writing peripheral register)
  6. NVIC pops 8 registers, returns to interrupted code (BXLR EXC_RETURN)

  SysTick: lowest recommended priority (0xE0 on Cortex-M4) — OS tick
  Hardfault/NMI: non-maskable; priority -3/-2/-1 fixed by hardware

ISR Implementation Rules

Cisr_rules.c

#include 
#include "Std_Types.h"

/* Rule 1: ISRs must be SHORT — offload work to tasks via flags/queues */
/* Rule 2: No blocking calls inside ISR (no OS waits, no delay loops) */
/* Rule 3: Shared variables must be volatile (and protected if multi-word) */
/* Rule 4: Clear the interrupt source BEFORE re-enabling interrupts */

/* Shared data between ISR and task */
volatile uint8_t  g_can_rx_pending = 0u;
volatile uint8_t  g_can_rx_data[8];
volatile uint8_t  g_can_rx_dlc = 0u;

/* Good ISR: minimal work, signals task via flag */
void CAN0_RX_IRQHandler(void)
{
    /* 1. Read data from peripheral (clears interrupt source) */
    uint8_t dlc = (uint8_t)(CAN0_RXMSG_REG & 0x0Fu);
    for (uint8_t i = 0u; i < dlc; i++) {
        g_can_rx_data[i] = (uint8_t)(CAN0_RXDATA_REG[i] & 0xFFu);
    }
    g_can_rx_dlc = dlc;

    /* 2. Signal task to process (set flag last — task reads data after flag) */
    g_can_rx_pending = 1u;

    /* 3. Acknowledge interrupt in NVIC (if edge-triggered) */
    NVIC_ClearPendingIRQ(CAN0_RX_IRQn);
}

/* Bad ISR: too much work, potential priority inversion */
/* void CAN0_RX_BAD_IRQHandler(void) {
     ParseCanMessage();    // BAD: complex processing in ISR
     OsMutexLock(&g_mutex); // BAD: OS mutex in ISR — deadlock risk
     NvM_WriteBlock(...);   // BAD: blocking NvM write
   }                                                              */

Interrupt Priority Configuration

Interrupt Source	Suggested Priority	Rationale
Safety shutdown (watchdog, voltage monitor)	0 (highest)	Must always pre-empt everything
Safety-critical ISR (brake, EPS)	16–32	Pre-empts normal ISRs
High-rate communication (Ethernet, CAN Tx/Rx)	48–64	Fast but below safety
Periodic OS tick (SysTick/STM)	80–96	Controls task scheduling
Slow peripherals (SPI, I2C complete)	112–128	Background operations
Diagnostic / logging	192–224	Lowest priority normal ISRs
SysTick (if using RTOS)	224–240	OS tick: lowest normal priority

Summary

NVIC priority configuration is an architectural decision that determines which real-time deadlines are met under load. Three rules: safety-critical ISRs always have higher priority than communication ISRs; no OS blocking calls inside any ISR; and ISR bodies should be as short as possible (read data, set flag, clear source). On Aurix TriCore, priorities are numbered opposite to Cortex-M (higher number = higher priority) — configuring the wrong value silently inverts priorities, causing subtle deadline misses that are difficult to reproduce.

🔬 Deep Dive — Core Concepts Expanded

This section builds on the foundational concepts covered above with additional technical depth, edge cases, and configuration nuances that separate competent engineers from experts. When working on production ECU projects, the details covered here are the ones most commonly responsible for integration delays and late-phase defects.

Key principles to reinforce:

Configuration over coding: In AUTOSAR and automotive middleware environments, correctness is largely determined by ARXML configuration, not application code. A correctly implemented algorithm can produce wrong results due to a single misconfigured parameter.
Traceability as a first-class concern: Every configuration decision should be traceable to a requirement, safety goal, or architecture decision. Undocumented configuration choices are a common source of regression defects when ECUs are updated.
Cross-module dependencies: In tightly integrated automotive software stacks, changing one module's configuration often requires corresponding updates in dependent modules. Always perform a dependency impact analysis before submitting configuration changes.

🏭 How This Topic Appears in Production Projects

Project integration phase: The concepts covered in this lesson are most commonly encountered during ECU integration testing — when multiple software components from different teams are combined for the first time. Issues that were invisible in unit tests frequently surface at this stage.
Supplier/OEM interface: This is a topic that frequently appears in technical discussions between Tier-1 ECU suppliers and OEM system integrators. Engineers who can speak fluently about these details earn credibility and are often brought into critical design review meetings.
Automotive tool ecosystem: Vector CANoe/CANalyzer, dSPACE tools, and ETAS INCA are the standard tools used to validate and measure the correct behaviour of the systems described in this lesson. Familiarity with these tools alongside the conceptual knowledge dramatically accelerates debugging in real projects.

⚠️ Common Mistakes and How to Avoid Them

Assuming default configuration is correct: Automotive software tools ship with default configurations that are designed to compile and link, not to meet project-specific requirements. Every configuration parameter needs to be consciously set. 'It compiled' is not the same as 'it is correctly configured'.
Skipping documentation of configuration rationale: In a 3-year ECU project with team turnover, undocumented configuration choices become tribal knowledge that disappears when engineers leave. Document why a parameter is set to a specific value, not just what it is set to.
Testing only the happy path: Automotive ECUs must behave correctly under fault conditions, voltage variations, and communication errors. Always test the error handling paths as rigorously as the nominal operation. Many production escapes originate in untested error branches.
Version mismatches between teams: In a multi-team project, the BSW team, SWC team, and system integration team may use different versions of the same ARXML file. Version management of all ARXML files in a shared repository is mandatory, not optional.

📊 Industry Note

Engineers who master both the theoretical concepts and the practical toolchain skills covered in this course are among the most sought-after professionals in the automotive software industry. The combination of AUTOSAR standards knowledge, safety engineering understanding, and hands-on configuration experience commands premium salaries at OEMs and Tier-1 suppliers globally.