Hands-On: ISR-Driven Communication

/* UART RX ring buffer: ISR writes, task reads — no critical section needed
   (single producer / single consumer pattern with proper memory ordering) */
#include 
#include "Std_Types.h"

#define RING_SIZE  256u  /* must be power of 2 */
#define RING_MASK  (RING_SIZE - 1u)

typedef struct {
    volatile uint8_t  buf[RING_SIZE];
    volatile uint16_t head;  /* written by ISR */
    volatile uint16_t tail;  /* written by task */
} RingBuffer_t;

static RingBuffer_t g_uart_rx;

/* ISR: called on each received byte (RXNE interrupt) */
void USART1_IRQHandler(void)
{
    uint8_t byte = (uint8_t)(USART1_DR & 0xFFu);  /* read clears RXNE flag */
    uint16_t next_head = (g_uart_rx.head + 1u) & RING_MASK;
    if (next_head != g_uart_rx.tail) {   /* not full: discard if full */
        g_uart_rx.buf[g_uart_rx.head] = byte;
        /* Write data before advancing head (memory ordering) */
        __DMB();
        g_uart_rx.head = next_head;
    }
}

/* Task: drain ring buffer */
boolean Uart_ReadByte(uint8_t *out)
{
    if (g_uart_rx.tail == g_uart_rx.head) { return FALSE; }  /* empty */
    *out = g_uart_rx.buf[g_uart_rx.tail];
    __DMB();
    g_uart_rx.tail = (g_uart_rx.tail + 1u) & RING_MASK;
    return TRUE;
}

uint16_t Uart_Available(void)
{
    return (uint16_t)((g_uart_rx.head - g_uart_rx.tail) & RING_MASK);
}

#include 
#include "Std_Types.h"

#define SPI_BUF_SIZE  128u

static uint8_t           g_spi_tx_buf[SPI_BUF_SIZE];
static uint8_t           g_spi_rx_buf[SPI_BUF_SIZE];
static volatile boolean  g_spi_dma_complete = FALSE;

/* DMA complete ISR */
void DMA1_CH3_IRQHandler(void)  /* SPI1 TX DMA channel */
{
    DMA1_SR |= DMA_IFCR_CTCIF3;   /* clear transfer complete flag */
    while (SPI1_SR & SPI_SR_BSY) {} /* wait for last bit to shift out */
    SPI1_CS_HIGH();                 /* deassert chip select */
    g_spi_dma_complete = TRUE;      /* signal task */
}

Std_ReturnType Spi_TransmitDMA(const uint8_t *data, uint8_t len)
{
    if (len > SPI_BUF_SIZE) { return E_NOT_OK; }

    /* Copy to DMA-accessible buffer (required if data is in non-DMA-accessible RAM) */
    for (uint8_t i = 0u; i < len; i++) { g_spi_tx_buf[i] = data[i]; }

    g_spi_dma_complete = FALSE;
    SPI1_CS_LOW();

    /* Configure DMA TX channel */
    DMA1_CH3->CPAR  = (uint32_t)&SPI1_DR;
    DMA1_CH3->CMAR  = (uint32_t)g_spi_tx_buf;
    DMA1_CH3->CNDTR = len;
    DMA1_CH3->CCR   = DMA_CCR_DIR | DMA_CCR_MINC | DMA_CCR_TCIE | DMA_CCR_EN;

    /* Enable SPI TX DMA request — peripheral drives DMA */
    SPI1_CR2 |= SPI_CR2_TXDMAEN;

    return E_OK;  /* returns immediately; DMA complete ISR signals completion */
}