Critical Sections & Atomic Operations

#include 
#include "cmsis_gcc.h"   /* __get_PRIMASK, __disable_irq, __enable_irq */

/* Pattern 1: Global interrupt disable/restore (Cortex-M) */
/* Save previous IRQ state (may already be disabled); disable; restore */
typedef uint32_t Critical_t;

static inline Critical_t Critical_Enter(void)
{
    Critical_t primask = __get_PRIMASK();   /* save current IRQ state */
    __disable_irq();                         /* disable all IRQs */
    __DSB();                                 /* data synchronisation barrier */
    return primask;
}

static inline void Critical_Exit(Critical_t saved)
{
    __DSB();
    if (saved == 0u) {
        __enable_irq();  /* only re-enable if IRQs were enabled before */
    }
}

/* Usage: */
volatile uint32_t g_shared_counter = 0u;

void increment_counter_safe(void)
{
    Critical_t state = Critical_Enter();
    g_shared_counter++;           /* atomic within critical section */
    Critical_Exit(state);
}

/* Pattern 2: BASEPRI masking (Cortex-M3/M4/M7) — mask only ISRs below threshold */
/* Allows high-priority safety ISRs to still fire during critical section */
static inline void Critical_EnterWithPriority(uint32_t priority)
{
    __set_BASEPRI(priority << (8u - __NVIC_PRIO_BITS));
    __DSB(); __ISB();
}
static inline void Critical_ExitPriority(void)
{
    __set_BASEPRI(0u);  /* re-enable all ISRs */
}

#include 
#include "cmsis_gcc.h"

/* LDREX/STREX: hardware exclusive monitor — lock-free atomic RMW */
/* Used for: atomic counters, lock-free queues, flag setting */

/* Atomic increment using LDREX/STREX (no interrupt disable needed) */
uint32_t atomic_increment(volatile uint32_t *ptr)
{
    uint32_t old_val, new_val;
    uint32_t result;
    do {
        old_val = __LDREXW(ptr);        /* load exclusive: set monitor */
        new_val = old_val + 1u;
        result  = __STREXW(new_val, ptr); /* store exclusive: 0=success, 1=fail */
        /* If another agent (ISR, other core) modified *ptr: STREX fails, retry */
    } while (result != 0u);
    return old_val;  /* returns previous value */
}

/* Atomic compare-and-swap */
uint32_t atomic_cas(volatile uint32_t *ptr, uint32_t expected, uint32_t new_val)
{
    uint32_t old_val = __LDREXW(ptr);
    if (old_val != expected) {
        __CLREX();  /* clear exclusive monitor without store */
        return old_val;
    }
    if (__STREXW(new_val, ptr) != 0u) {
        return atomic_cas(ptr, expected, new_val);  /* retry on contention */
    }
    return old_val;
}

/* C11 _Atomic (available in GCC for Cortex-M): compiler-generated LDREX/STREX */
#include 
atomic_uint g_event_flags = ATOMIC_VAR_INIT(0u);
void set_event_atomic(uint32_t evt) { atomic_fetch_or(&g_event_flags, evt); }
uint32_t get_and_clear_events(void) { return atomic_exchange(&g_event_flags, 0u); }

#include 

/* Problem: a 64-bit timestamp cannot be written atomically on 32-bit Cortex-M */
/* If ISR reads between the two 32-bit writes: reads half old, half new */

typedef struct {
    uint32_t lo;   /* lower 32 bits */
    uint32_t hi;   /* upper 32 bits */
} Timestamp64_t;

volatile Timestamp64_t g_timestamp;

/* Writer (task): update 64-bit timestamp */
void update_timestamp(uint64_t new_ts)
{
    Critical_t state = Critical_Enter();
    g_timestamp.lo = (uint32_t)(new_ts & 0xFFFFFFFFu);
    g_timestamp.hi = (uint32_t)(new_ts >> 32u);
    Critical_Exit(state);
}

/* Reader (ISR or task): read 64-bit timestamp consistently */
uint64_t read_timestamp(void)
{
    uint32_t lo, hi1, hi2;
    /* Double-read technique: detect roll-over during read */
    do {
        hi1 = g_timestamp.hi;   /* read hi first */
        lo  = g_timestamp.lo;   /* read lo */
        hi2 = g_timestamp.hi;   /* read hi again */
    } while (hi1 != hi2);       /* if hi changed: lo may be from new epoch; retry */

    return ((uint64_t)hi1 << 32u) | (uint64_t)lo;
}