Shared Memory & Race Condition Detection

// MCDS multi-core write watchpoint: catch concurrent writes to shared variable

MCDS.ON

// Set write watchpoint on both cores simultaneously for same address
CORE.select 1.
Break.Set g_sharedCounter /Write /Hardware /CORE 1.  // Core0 write trigger

CORE.select 2.
Break.Set g_sharedCounter /Write /Hardware /CORE 2.  // Core1 write trigger

// Cross-trigger: if BOTH cores write within 100ns → halt all cores
// This catches the race window
MCDS.Trigger.Window g_sharedCounter /Write /AllCores /Window 100ns

Go
WAIT !STATE.RUN() 30s   // wait for concurrent write race

// On halt: both cores halted; inspect their contexts
CORE.select 1.
Frame.view /Caller
PRINT "Core0 was at: " FORMAT.ADDRESS(Register(PC))

CORE.select 2.
Frame.view /Caller
PRINT "Core1 was at: " FORMAT.ADDRESS(Register(PC))

// Both call stacks will point to the non-atomic RMW code — found the race

/* Aurix TriCore LDMST (Load-Modify-Store Atomic) instruction */
/* No spinlock needed for single-word shared counter updates */
#include 
#include 

/* WRONG: Non-atomic read-modify-write (race condition): */
void Counter_IncrementRacy(volatile uint32_t *counter) {
    (*counter)++;  /* compiles to LOAD + ADD + STORE: not atomic */
}

/* CORRECT: TriCore atomic add using LDMST intrinsic */
void Counter_IncrementAtomic(volatile uint32_t *counter) {
    /* __LDMST: atomic load-modify-store with AND mask + OR value
       mask=0 means "replace lower 16 bits with value"
       For simple increment: use __SWAPMSK or GCC __sync_fetch_and_add */
    __sync_fetch_and_add(counter, 1u);  /* GCC built-in: emits LDMST */
}

/* For larger shared data structures: spinlock (AUTOSAR SpinlockIdType) */
void SharedStruct_Update(SharedData_t *data, uint32_t new_val) {
    GetSpinlock(SPINLOCK_SHARED_DATA);   /* AUTOSAR OS API */
    data->value = new_val;
    data->version++;
    ReleaseSpinlock(SPINLOCK_SHARED_DATA);
}

/* TRACE32 verification: confirm LDMST in disassembly
   Data.LOAD.Elf ...; List Counter_IncrementAtomic
   → should show: LDMST [A4], E4  (single atomic instruction) */