Home Learning Paths ECU Lab Assessments Interview Preparation Arena Pricing Log In Sign Up

Lab Setup

ItemRequirement
TargetAurix TC397 board; 300 MHz core clock
ProbeLauterbach iC5000 (MCDS trace) or LA-7780 (ETM)
Lab ELFtiming_lab.elf — contains an intentionally slow OsTask_10ms and a cache-thrashing data structure
Expected baselineOsTask_10ms avg 7.8ms, max 14.2ms (budget: 10ms — violation on every cycle)

Exercise 1: Identify the Overrunning Function

CMMtiming_ex1.cmm
// Step 1: STM profiling — coarse-grained identification
// Add PROF_START/END to each runnable temporarily
// Or: use ETM profiling without any source modification

ETM.ON
ETM.DataTrace NONE
Trace.METHOD Analyzer
Trace.Size 64MB

Go
WAIT 2s
Break

// Generate flat profile
Trace.Statistics.Func /MAX
// Expected output (sorted by total time):
// 1. NvM_MainFunction         43.2%   avg=4.2ms  max=12.1ms  calls=10
// 2. Can_MainFunction          18.3%   avg=1.8ms  max=3.2ms   calls=10
// 3. Com_MainFunction           7.1%   avg=0.7ms  max=0.9ms   calls=10
//
// NvM_MainFunction worst-case 12.1ms in a 10ms task → violation culprit

// Drill into NvM: which NvM operations are slow?
Trace.Statistics.Func "NvM*"    // wildcard: all NvM_ functions
// NvM_WriteBlock called with 1024-byte block per cycle — excessive

Exercise 2: Cache Thrashing in Data Table

CMMtiming_ex2.cmm
// Step 2: MCDS cache miss analysis
MCDS.ON
MCDS.PerfCounter DMISS
MCDS.PerfCounter.RESET

// Profile only NvM_MainFunction
Break.Set NvM_MainFunction /Program
Go ; WAIT !STATE.RUN() 2s
LOCAL &t_start
&t_start=Data.Long(SFR:STM0.TIM0)
MCDS.PerfCounter.RESET
Go NvM_Return    // run to return
WAIT !STATE.RUN() 50ms

LOCAL &dmiss &duration
&dmiss=MCDS.PerfCounter.VALUE(DMISS)
&duration=(Data.Long(SFR:STM0.TIM0)-&t_start)/300.
PRINT "NvM DCACHE misses: " &dmiss " in " FORMAT.FLOAT(2.,1.,&duration) " µs"
// Expected: 4800 D-cache misses in 4200µs = ~1.14 misses/µs
// Each miss: ~30-cycle bus stall = ~100ns → 480µs lost to cache misses

// Inspect data structure layout
Var.View %Size (NvM_BlockDescriptor_t *)g_nvmBlocks
// Each descriptor: 128 bytes; array of 64 = 8192 bytes = 256 cache lines
// Access pattern: random by block ID → poor spatial locality → high miss rate

// Fix: sort blocks by access frequency; pack hot fields to first 32 bytes per struct

Exercise 3: Apply Fix and Verify Improvement

CMMtiming_ex3.cmm
// After fix: NvM descriptors reordered (hot fields first + sorted by access frequency)
// Rebuild and reflash: aurix_pflash.cmm with new ELF

Data.LOAD.Elf timing_lab_fixed.elf
SYStem.Reset

// Re-run ETM profile with fixed code
ETM.ON
Trace.METHOD Analyzer
Trace.Size 64MB
Go
WAIT 2s
Break

// Compare profiles
Trace.Statistics.Func /MAX
// Expected after fix:
// 1. NvM_MainFunction  22.1%  avg=2.1ms  max=3.4ms  (was avg=4.2ms max=12.1ms)
// 2. Can_MainFunction  18.3%  avg=1.8ms  max=3.2ms  (unchanged)

// Verify task timing now within budget
Trace.Chart.TASK
// OsTask_10ms now stays comfortably under 10ms on every activation

// Run 1000 cycles to confirm no residual overruns
LOCAL &overruns
&overruns=0.
LOCAL &i
&i=0.
WHILE &i<1000.
(
    Go OsTask_10ms_Entry ; WAIT !STATE.RUN() 100ms
    LOCAL &t1
    &t1=Data.Long(SFR:STM0.TIM0)
    Go OsTask_10ms_Exit  ; WAIT !STATE.RUN() 100ms
    LOCAL &t2
    &t2=Data.Long(SFR:STM0.TIM0)
    IF (&t2-&t1)>3000000.   // 10ms in 300MHz ticks
        &overruns=&overruns+1.
    &i=&i+1.
)
PRINT "Overruns in 1000 cycles: " &overruns " (expected: 0)" 

Summary

Two-stage timing investigation: coarse ETM flat profile identified NvM_MainFunction as the culprit in under 2 minutes without source modification; MCDS D-cache miss counter pinpointed cache thrashing as the mechanism. The fix — struct field reordering and access-frequency sorting — reduced NvM avg execution time from 4.2ms to 2.1ms (50% improvement) with zero algorithm change. The 1000-cycle regression loop confirms zero residual overruns. This workflow is applicable to any task that exceeds its timing budget.

🔬 Deep Dive — Core Concepts Expanded

This section builds on the foundational concepts covered above with additional technical depth, edge cases, and configuration nuances that separate competent engineers from experts. When working on production ECU projects, the details covered here are the ones most commonly responsible for integration delays and late-phase defects.

Key principles to reinforce:

  • Configuration over coding: In AUTOSAR and automotive middleware environments, correctness is largely determined by ARXML configuration, not application code. A correctly implemented algorithm can produce wrong results due to a single misconfigured parameter.
  • Traceability as a first-class concern: Every configuration decision should be traceable to a requirement, safety goal, or architecture decision. Undocumented configuration choices are a common source of regression defects when ECUs are updated.
  • Cross-module dependencies: In tightly integrated automotive software stacks, changing one module's configuration often requires corresponding updates in dependent modules. Always perform a dependency impact analysis before submitting configuration changes.

🏭 How This Topic Appears in Production Projects

  • Project integration phase: The concepts covered in this lesson are most commonly encountered during ECU integration testing — when multiple software components from different teams are combined for the first time. Issues that were invisible in unit tests frequently surface at this stage.
  • Supplier/OEM interface: This is a topic that frequently appears in technical discussions between Tier-1 ECU suppliers and OEM system integrators. Engineers who can speak fluently about these details earn credibility and are often brought into critical design review meetings.
  • Automotive tool ecosystem: Vector CANoe/CANalyzer, dSPACE tools, and ETAS INCA are the standard tools used to validate and measure the correct behaviour of the systems described in this lesson. Familiarity with these tools alongside the conceptual knowledge dramatically accelerates debugging in real projects.

⚠️ Common Mistakes and How to Avoid Them

  1. Assuming default configuration is correct: Automotive software tools ship with default configurations that are designed to compile and link, not to meet project-specific requirements. Every configuration parameter needs to be consciously set. 'It compiled' is not the same as 'it is correctly configured'.
  2. Skipping documentation of configuration rationale: In a 3-year ECU project with team turnover, undocumented configuration choices become tribal knowledge that disappears when engineers leave. Document why a parameter is set to a specific value, not just what it is set to.
  3. Testing only the happy path: Automotive ECUs must behave correctly under fault conditions, voltage variations, and communication errors. Always test the error handling paths as rigorously as the nominal operation. Many production escapes originate in untested error branches.
  4. Version mismatches between teams: In a multi-team project, the BSW team, SWC team, and system integration team may use different versions of the same ARXML file. Version management of all ARXML files in a shared repository is mandatory, not optional.

📊 Industry Note

Engineers who master both the theoretical concepts and the practical toolchain skills covered in this course are among the most sought-after professionals in the automotive software industry. The combination of AUTOSAR standards knowledge, safety engineering understanding, and hands-on configuration experience commands premium salaries at OEMs and Tier-1 suppliers globally.

← PreviousCache & Pipeline AnalysisNext →Symmetric & Asymmetric Multi-Core Debug