Hands-On: Multi-Core Issue Resolution

// Use MCDS windowed watchpoint to catch the race in hardware

MCDS.ON
SYStem.Option CORESHARING ON   // synchronised halt across all cores

// Core0 write watchpoint
CORE.select 1.
Break.Set g_canRxCount /Write /Hardware /CORE 1.

// Core2 write watchpoint
CORE.select 3.
Break.Set g_canRxCount /Write /Hardware /CORE 3.

// Cross-core trigger: halt ALL cores if Core0 and Core2 write within 500ns
MCDS.Trigger.Window g_canRxCount /Write /AllCores /Window 500ns

PRINT "Running — waiting for race condition..."
Go
WAIT !STATE.RUN() 60s          // race: may take many seconds; run long enough

IF STATE.RUN()
(
    PRINT "Race NOT detected in 60s — verify watchpoints are configured correctly"
)
ELSE
(
    PRINT "RACE DETECTED at PC=" FORMAT.ADDRESS(Register(PC))
    CORE.select 1. ; PRINT "Core0: " FORMAT.ADDRESS(Register(PC))
    CORE.select 3. ; PRINT "Core2: " FORMAT.ADDRESS(Register(PC))
    Frame.view /Caller   // show which function caused the write on Core2
)

// After reflashing with atomic increment fix:
// g_canRxCount++ replaced with __sync_fetch_and_add(&g_canRxCount, 1)

// 1. Verify LDMST in disassembly (not LOAD+ADD+STORE)
Data.LOAD.Elf multicore_lab_fixed.elf
List.Mix CAN_RxIndication        // disassembly of fixed function
// Expected: single LDMST instruction at the counter update

// 2. Re-run MCDS race detector — expect zero trigger in 10,000 cycles
MCDS.ON
MCDS.Trigger.Window g_canRxCount /Write /AllCores /Window 500ns

Go
WAIT 30s           // 30s = ~3000 10ms task cycles
Break

PRINT "Race triggers detected: " MCDS.Trigger.COUNT()
IF MCDS.Trigger.COUNT()==0.
    PRINT "PASS: No races detected after atomic fix"
ELSE
    PRINT %ERROR "FAIL: " MCDS.Trigger.COUNT() " race(s) still detected"

// 3. Verify counter value accuracy
LOCAL &rx_expected &rx_actual
&rx_expected=Data.Long(SFR:CAN0.SR) & 0xFFFF  // HW frame count from CAN module
&rx_actual=Var.VALUE(g_canRxCount)
PRINT "HW count: " &rx_expected " SW count: " &rx_actual
IF &rx_actual==&rx_expected
    PRINT "PASS: SW counter matches HW counter"
ELSE
    PRINT %ERROR "FAIL: counter mismatch by " (&rx_expected-&rx_actual)

// Measure spinlock contention: how often does Core0 spin waiting for Core2?
// Instrumented SpinLock_Acquire: counts spin iterations before lock acquired

// STM-based spinlock wait time measurement
PROF_START macro at SpinLock_Acquire entry
PROF_END macro at first acquired state

// After 1000 cycles, check profiling slots:
Go
WAIT 10s
Break
Var.View g_spinlockProfSlot     // shows min/max/avg wait time for spinlock

// High max spinlock wait = Core2 holds lock for too long during CAN ISR
// Fix: shorten critical section in CAN ISR; don't call BSW functions under spinlock

// Check for deadlock risk: both cores waiting for same spinlock
Var.View g_spinlockHolders      // which core currently holds each spinlock
// If g_spinlockHolders[SPINLOCK_IPC] == Core0 AND Core0 is waiting -> deadlock