Cross-Core Breakpoints & Sync - Debugging & Tracing

Cross-Core Trigger Architecture on Aurix TC3xx

Aurix Cross Triggering Unit (OTGS/BCTM)

  Core0 debug trigger (breakpoint, watchpoint, ETM trigger)
       │  → fires OTGS trigger channel 0
       ▼
  OTGS (On-chip Trigger and Gate System)
  ├── Trigger routing matrix: any core trigger can gate any other core's halt
  ├── Trigger channel 0 → halt Core1 simultaneously
  ├── Trigger channel 0 → start/stop MCDS trace on Core1
  └── Trigger channel 0 → GPIO pin toggle (scope trigger for mixed-signal debug)

  BCTM (Break Controller and Trigger Matrix):
  ├── Core0 hardware BP hit → BCTM broadcasts HALT to all other cores
  ├── All cores halted within ≤ 2 clock cycles of trigger
  └── Ensures consistent snapshot: Core1 and Core2 stopped at known state

Synchronous Multi-Core Breakpoints

CMMcross_core_bp.cmm

// Cross-core synchronous halt: Core0 BP halts all cores together

// Step 1: Enable cross-trigger (BCTM global halt)
SYStem.Option CORESHARING ON    // Aurix: shares halt signals between cores

// Step 2: Set breakpoint on Core0
CORE.select 1.
Break.Set Ipc_SendMessage /Program  // Core0 sends IPC message

// Step 3: When Core0 hits BP, verify Core1 state at same moment
// TRACE32 automatically halts Core1 via BCTM cross-trigger

// View Core1 state at the instant Core0 was in Ipc_SendMessage
CORE.select 2.
Frame.view /Caller              // Core1 call stack at halt moment
Var.View g_ipcQueue             // IPC queue state at atomic snapshot

// Cross-trigger condition: halt Core0 only when Core1 has processed N messages
// MCDS comparator on Core1 counter triggers Core0 halt
MCDS.ON
MCDS.Trigger.CrossCore 1. 2. "g_ipcRxCount == 100"  // Core1 condition → Core0 halt

Go
WAIT !STATE.RUN() 30s           // wait for condition on Core1

Debugging IPC Protocols Between Cores

Cipc_debug.c

/* IPC debug instrumentation: trace cross-core message queue */
#include "SpinLock.h"
#include 

/* Circular buffer in LMU RAM — accessible from all cores */
#define IPC_QUEUE_SIZE 16u

typedef struct {
    uint32_t msg_id;
    uint32_t payload;
    uint32_t sender_core;
    uint32_t timestamp_stm;   /* STM tick at send time */
} IpcMsg_t;

typedef struct {
    IpcMsg_t   msgs[IPC_QUEUE_SIZE];
    uint32_t   head;
    uint32_t   tail;
    uint32_t   overflow_count;
} IpcQueue_t;

/* LMU placement: accessible from all 3 cores */
__attribute__((section(".data.lmu")))
volatile IpcQueue_t g_ipcQueue;

/* In TRACE32: watch g_ipcQueue continuously to monitor IPC activity
   Var.Watch %Open %Hex g_ipcQueue
   Data.dump g_ipcQueue.msgs[0..15] /Struct  */

void IPC_Send(uint32_t core_id, uint32_t msg_id, uint32_t payload) {
    SpinLock_Acquire(SPINLOCK_IPC);
    uint32_t next = (g_ipcQueue.head + 1u) % IPC_QUEUE_SIZE;
    if (next != g_ipcQueue.tail) {
        g_ipcQueue.msgs[g_ipcQueue.head].msg_id       = msg_id;
        g_ipcQueue.msgs[g_ipcQueue.head].payload      = payload;
        g_ipcQueue.msgs[g_ipcQueue.head].sender_core  = core_id;
        g_ipcQueue.msgs[g_ipcQueue.head].timestamp_stm= (uint32_t)MODULE_STM0.TIM0.U;
        g_ipcQueue.head = next;
    } else {
        g_ipcQueue.overflow_count++;  /* TRACE32 watchpoint on overflow_count! */
    }
    SpinLock_Release(SPINLOCK_IPC);
}

Summary

The OTGS/BCTM cross-trigger system on Aurix TC3xx halts all cores within 2 clock cycles of a trigger — a 300 MHz clock gives a 6.7 ns worst-case skew between core halt times. This is tight enough to treat the multi-core snapshot as effectively simultaneous for debugging purposes. IPC queue overflow_count is the fastest field to watchpoint: a DWT watchpoint on g_ipcQueue.overflow_count triggers immediately when any core fails to drain the queue fast enough, pointing directly to the receiver that is too slow.

🔬 Deep Dive — Core Concepts Expanded

This section builds on the foundational concepts covered above with additional technical depth, edge cases, and configuration nuances that separate competent engineers from experts. When working on production ECU projects, the details covered here are the ones most commonly responsible for integration delays and late-phase defects.

Key principles to reinforce:

Configuration over coding: In AUTOSAR and automotive middleware environments, correctness is largely determined by ARXML configuration, not application code. A correctly implemented algorithm can produce wrong results due to a single misconfigured parameter.
Traceability as a first-class concern: Every configuration decision should be traceable to a requirement, safety goal, or architecture decision. Undocumented configuration choices are a common source of regression defects when ECUs are updated.
Cross-module dependencies: In tightly integrated automotive software stacks, changing one module's configuration often requires corresponding updates in dependent modules. Always perform a dependency impact analysis before submitting configuration changes.

🏭 How This Topic Appears in Production Projects

Project integration phase: The concepts covered in this lesson are most commonly encountered during ECU integration testing — when multiple software components from different teams are combined for the first time. Issues that were invisible in unit tests frequently surface at this stage.
Supplier/OEM interface: This is a topic that frequently appears in technical discussions between Tier-1 ECU suppliers and OEM system integrators. Engineers who can speak fluently about these details earn credibility and are often brought into critical design review meetings.
Automotive tool ecosystem: Vector CANoe/CANalyzer, dSPACE tools, and ETAS INCA are the standard tools used to validate and measure the correct behaviour of the systems described in this lesson. Familiarity with these tools alongside the conceptual knowledge dramatically accelerates debugging in real projects.

⚠️ Common Mistakes and How to Avoid Them

Assuming default configuration is correct: Automotive software tools ship with default configurations that are designed to compile and link, not to meet project-specific requirements. Every configuration parameter needs to be consciously set. 'It compiled' is not the same as 'it is correctly configured'.
Skipping documentation of configuration rationale: In a 3-year ECU project with team turnover, undocumented configuration choices become tribal knowledge that disappears when engineers leave. Document why a parameter is set to a specific value, not just what it is set to.
Testing only the happy path: Automotive ECUs must behave correctly under fault conditions, voltage variations, and communication errors. Always test the error handling paths as rigorously as the nominal operation. Many production escapes originate in untested error branches.
Version mismatches between teams: In a multi-team project, the BSW team, SWC team, and system integration team may use different versions of the same ARXML file. Version management of all ARXML files in a shared repository is mandatory, not optional.

📊 Industry Note

Engineers who master both the theoretical concepts and the practical toolchain skills covered in this course are among the most sought-after professionals in the automotive software industry. The combination of AUTOSAR standards knowledge, safety engineering understanding, and hands-on configuration experience commands premium salaries at OEMs and Tier-1 suppliers globally.