Bit Timing & Baud Rate Calculation - Vehicle Networks

Bit Time Segment Structure

CAN Bit Time Segments

  ←──────────────── 1 Bit Time ──────────────────→
  ┌──────┬───────────────┬──────────────┬──────────┐
  │ Sync │   Prop_Seg    │  Phase_Seg1  │Phase_Seg2│
  │  1tq │   1–8 tq      │   1–8 tq     │  1–8 tq  │
  └──────┴───────────────┴──────────────┴──────────┘
                                        ↑
                                   Sample Point
                              (end of Phase_Seg1)

  tq (time quantum) = CAN clock period × prescaler
  Total bit time = (1 + Prop + Ph1 + Ph2) × tq
  Baud rate = 1 / total bit time

Segment	Duration	Purpose
Sync_Seg	1 tq fixed	Expected edge for hard synchronisation (SOF)
Prop_Seg	1–8 tq	Compensates for bus propagation delay (twice the physical delay)
Phase_Seg1	1–8 tq	Can be lengthened by SJW during resynchronisation
Phase_Seg2	1–8 tq	Can be shortened by SJW; determines output signal timing

Baud Rate Calculation Examples

Pythonbit_timing_calculator.py

# CAN bit timing calculator
# Input: MCU CAN clock, target baud rate, desired sample point %

def calculate_bit_timing(can_clock_hz, target_baud, sample_point_pct=80):
    results = []
    for prescaler in range(1, 65):
        tq_ns = (1 / can_clock_hz) * prescaler * 1e9
        total_tq = round(1e9 / (target_baud * tq_ns))
        if not (8 <= total_tq <= 25):  # practical range
            continue
        ph2 = round(total_tq * (1 - sample_point_pct / 100))
        ph2 = max(1, min(8, ph2))
        remaining = total_tq - 1 - ph2  # subtract Sync_Seg
        prop = max(1, remaining // 2)
        ph1  = remaining - prop
        if 1 <= ph1 <= 8 and 1 <= prop <= 8:
            actual_baud = 1e9 / (tq_ns * total_tq)
            actual_sp   = (1 + prop + ph1) / total_tq * 100
            error_ppm   = abs(actual_baud - target_baud) / target_baud * 1e6
            results.append((prescaler, prop, ph1, ph2, actual_baud, actual_sp, error_ppm))
    return sorted(results, key=lambda r: r[6])  # sort by baud error

# Example: STM32 at 42 MHz → 500 kbps
for r in calculate_bit_timing(42_000_000, 500_000)[:3]:
    pre, prop, ph1, ph2, baud, sp, err = r
    print(f"Prescaler={pre} Prop={prop} Ph1={ph1} Ph2={ph2} "
          f"→ {baud/1000:.1f} kbps SP={sp:.1f}% error={err:.1f} ppm")

MCU Clock	Prescaler	Prop+Ph1+Ph2 (tq)	Baud Rate	Sample Point
48 MHz	6	1+5+2 (8 tq per bit)	1 Mbps	75%
48 MHz	6	3+8+3 (14 tq per bit)	571 kbps	—
40 MHz	4	4+7+2 (13 tq per bit + 1 sync = 10 tq total)	1 Mbps	80%
80 MHz	8	4+7+3 (14 tq per bit + 1 = 15 total)	666 kbps	—

Sample Point Positioning

💡 Why Sample Point Matters

The sample point is where the CAN controller reads the bus state to determine the received bit value. Too early (e.g., 60%) and the node may sample before the bus has settled after propagation delays from a distant transmitter. Too late (e.g., 90%) and there is insufficient time for resynchronisation — the node cannot shift Phase_Seg2 to compensate for an oscillator that is running slightly fast. The industry recommendation of 75–87.5% is a balance between settling time and resync margin.

Sample Point %	Risk if Too Low	Risk if Too High
< 65%	Sampling before bus settles → intermittent errors on long buses	—
75–87.5%	— (recommended range)	—
> 90%	—	Insufficient Phase_Seg2 for resynchronisation → errors at high bus loads

Resynchronisation and SJW

Resynchronisation: Phase Error Correction

  Expected bit edge (from local clock):  ─────┐
                                               │
  Actual bus edge (arrives late):          ────┼──┐
                                               │  │ phase error e
                                               │  │
  SJW (Synchronisation Jump Width):            └──┘ = max correction
  Phase_Seg1 is lengthened by min(e, SJW) to delay the sample point
  Phase_Seg2 can be shortened by min(e, SJW) for early edge

  SJW = 1–4 tq; larger SJW = more tolerance for oscillator deviation
  but reduces the proportion of bit time available for data

SJW Value	Max Oscillator Tolerance	Trade-off
1 tq	±0.1% frequency deviation	Minimal; sufficient for good-quality oscillators
2 tq	±0.2%	Standard for most automotive ECUs
4 tq	±0.4%	Maximum; for long buses or poor-quality oscillators

Summary

Bit timing is the most common source of intermittent CAN communication errors in new hardware bring-up. Always use a calculator tool (Vector Hardware Configurator, online Bittiming Calculator) rather than manual trial-and-error. Validate the timing on the actual hardware with a CAN analyser: check that the sample point in the trace matches the configured percentage and that TEC/REC stay at zero under 80% bus load.

🔬 Deep Dive — Core Concepts Expanded

This section builds on the foundational concepts covered above with additional technical depth, edge cases, and configuration nuances that separate competent engineers from experts. When working on production ECU projects, the details covered here are the ones most commonly responsible for integration delays and late-phase defects.

Key principles to reinforce:

Configuration over coding: In AUTOSAR and automotive middleware environments, correctness is largely determined by ARXML configuration, not application code. A correctly implemented algorithm can produce wrong results due to a single misconfigured parameter.
Traceability as a first-class concern: Every configuration decision should be traceable to a requirement, safety goal, or architecture decision. Undocumented configuration choices are a common source of regression defects when ECUs are updated.
Cross-module dependencies: In tightly integrated automotive software stacks, changing one module's configuration often requires corresponding updates in dependent modules. Always perform a dependency impact analysis before submitting configuration changes.

🏭 How This Topic Appears in Production Projects

Project integration phase: The concepts covered in this lesson are most commonly encountered during ECU integration testing — when multiple software components from different teams are combined for the first time. Issues that were invisible in unit tests frequently surface at this stage.
Supplier/OEM interface: This is a topic that frequently appears in technical discussions between Tier-1 ECU suppliers and OEM system integrators. Engineers who can speak fluently about these details earn credibility and are often brought into critical design review meetings.
Automotive tool ecosystem: Vector CANoe/CANalyzer, dSPACE tools, and ETAS INCA are the standard tools used to validate and measure the correct behaviour of the systems described in this lesson. Familiarity with these tools alongside the conceptual knowledge dramatically accelerates debugging in real projects.

⚠️ Common Mistakes and How to Avoid Them

Assuming default configuration is correct: Automotive software tools ship with default configurations that are designed to compile and link, not to meet project-specific requirements. Every configuration parameter needs to be consciously set. 'It compiled' is not the same as 'it is correctly configured'.
Skipping documentation of configuration rationale: In a 3-year ECU project with team turnover, undocumented configuration choices become tribal knowledge that disappears when engineers leave. Document why a parameter is set to a specific value, not just what it is set to.
Testing only the happy path: Automotive ECUs must behave correctly under fault conditions, voltage variations, and communication errors. Always test the error handling paths as rigorously as the nominal operation. Many production escapes originate in untested error branches.
Version mismatches between teams: In a multi-team project, the BSW team, SWC team, and system integration team may use different versions of the same ARXML file. Version management of all ARXML files in a shared repository is mandatory, not optional.

📊 Industry Note

Engineers who master both the theoretical concepts and the practical toolchain skills covered in this course are among the most sought-after professionals in the automotive software industry. The combination of AUTOSAR standards knowledge, safety engineering understanding, and hands-on configuration experience commands premium salaries at OEMs and Tier-1 suppliers globally.