Core Partitioning Strategies - AUTOSAR Expert

ASIL Decomposition by Core

ISO 26262-6 permits spatial separation between an ASIL-D function and a QM function as evidence of Freedom from Interference (FFI), provided the separation is enforced by an independent mechanism (MPU hardware). Placing each on a dedicated OsCore with separate OsApplication + MPU regions is the standard implementation pattern.

ASIL Core Partitioning

  Core 0 — ASIL-B/D Partition                Core 1 — QM Partition
  ┌───────────────────────────────┐           ┌──────────────────────────────┐
  │ OsApp_Safety (non-trusted)    │           │ OsApp_QM (trusted)           │
  │  Task_SafetyCtrl_10ms         │           │  Task_ComStack_1ms           │
  │  EPS_SWC, BrakeCtrl_SWC      │           │  COM, PduR, CanIf            │
  │  WdgM, PHM supervision        │           │  Task_ADAS_50ms              │
  ├───────────────────────────────┤           ├──────────────────────────────┤
  │ OsApp_BSW_Safety (trusted)    │           │ OsApp_BSW_QM (trusted)       │
  │  EcuM, BswM, DEM, NvM        │           │  DCM, FIM                    │
  └───────────────────────────────┘           └──────────────────────────────┘
  MPU enforces: Safety .data inaccessible     MPU: QM tasks cannot write
  from QM core via hardware                   to Safety .data regions

ASIL Level	Core Assignment	OsApplication Type	MPU Enforcement
ASIL-D	Core 0 dedicated	Non-trusted (MPU restricted)	Hardware MPU blocks cross-OsApp writes
ASIL-B (decomposed)	Core 0 or dedicated	Non-trusted	MPU + OsTaskTimeFrame
QM	Core 1	Trusted or Non-trusted	Trusted = full memory access (BSW); Non-trusted for SWCs

Peripheral Ownership Rules

MCAL drivers access hardware registers directly. Concurrent register access from two cores without hardware arbitration causes undefined hardware behaviour. AUTOSAR CP enforces single-core ownership per peripheral.

Peripheral / Module	Owner Core	Rationale
CanDrv, CanIf	Core 0	CAN controller registers on Core 0; ISR routed to Core 0
EthDrv, EthIf	Core 1	Ethernet DMA on Core 1; high Rx bandwidth offloaded from safety core
SpiDrv, FlsDrv, Fee, NvM	Core 0	Flash SPI bus single-master; NvM is a singleton BSW module
AdcDrv	Core 0	ADC channels shared; single sequencer; results DMA to Core 0 RAM
PwmDrv	Core 0	PWM timer registers on Core 0; actuator outputs on safety core

⚠️ No Shared Register Access

If two BSW modules on different cores must both access the same hardware peripheral (e.g., a shared SPI bus used by both Fee and an external sensor driver), one module must own the hardware and the other must request access via a BSW service port or spinlock-protected request queue. Never access the same peripheral from two cores simultaneously — even read-only register access can trigger hardware fault conditions on some microcontrollers.

BSW Singleton vs Distributed Modules

BSW Module	Deployment	Reason
NvM	Singleton on Core 0	State machine not thread-safe; Fee/Fls on Core 0
DEM	Singleton on Core 0	DTC storage in NvM; FIM callbacks from any core use IOC to report
EcuM, BswM	Singleton on Core 0	Master boot controller; wakeup/sleep arbitration
WdgM	Singleton on Core 0	Hardware watchdog triggered from Core 0 only
COM	Distributable per cluster	Each CAN cluster's COM instance on the core owning CanIf for that cluster
PduR	Distributable per cluster	Routing table split per network cluster, same core as COM
DCM	Singleton on Core 0	Uses DEM and NvM APIs — all on Core 0

Load Analysis with Timing Architects TA Tool Suite

Pythonta_load_model.py

# Example: model task WCET per core in TA Tool Suite Python API
import ta_toolsuite as ta

model = ta.load_project("ECU_MultiCore.taprj")

# Set WCET per task (from TRACE32 runtime measurements)
model.set_wcet("Task_SafetyCtrl_10ms", core=0, wcet_us=350)
model.set_wcet("Task_ComStack_1ms",    core=1, wcet_us=180)
model.set_wcet("Task_ADAS_50ms",       core=1, wcet_us=8000)

# Run schedulability analysis
result = model.analyze_schedulability()

for core_id, core_result in result.items():
    print(f"Core {core_id}: utilisation={core_result.utilisation:.1%}")
    for task in core_result.infeasible_tasks:
        print(f"  INFEASIBLE: {task.name} misses deadline by {task.slack_us} us")

# Output example:
# Core 0: utilisation=72.4%
# Core 1: utilisation=91.8%
#   INFEASIBLE: Task_ADAS_50ms misses deadline by 320 us

Summary

Core partitioning is an architectural decision with safety, performance, and hardware implications that must be made before any BSW configuration begins. The rule is simple: one core owns each hardware peripheral, safety SWCs on a dedicated ASIL core with MPU isolation, BSW singletons (NvM, DEM, EcuM) on Core 0, and distributable modules (COM, PduR) on whichever core owns the corresponding MCAL. Validate the partition with a TA Tool Suite schedulability analysis before the first hardware board is available.

🔬 Deep Dive — Core Concepts Expanded

This section builds on the foundational concepts covered above with additional technical depth, edge cases, and configuration nuances that separate competent engineers from experts. When working on production ECU projects, the details covered here are the ones most commonly responsible for integration delays and late-phase defects.

Key principles to reinforce:

Configuration over coding: In AUTOSAR and automotive middleware environments, correctness is largely determined by ARXML configuration, not application code. A correctly implemented algorithm can produce wrong results due to a single misconfigured parameter.
Traceability as a first-class concern: Every configuration decision should be traceable to a requirement, safety goal, or architecture decision. Undocumented configuration choices are a common source of regression defects when ECUs are updated.
Cross-module dependencies: In tightly integrated automotive software stacks, changing one module's configuration often requires corresponding updates in dependent modules. Always perform a dependency impact analysis before submitting configuration changes.

🏭 How This Topic Appears in Production Projects

Project integration phase: The concepts covered in this lesson are most commonly encountered during ECU integration testing — when multiple software components from different teams are combined for the first time. Issues that were invisible in unit tests frequently surface at this stage.
Supplier/OEM interface: This is a topic that frequently appears in technical discussions between Tier-1 ECU suppliers and OEM system integrators. Engineers who can speak fluently about these details earn credibility and are often brought into critical design review meetings.
Automotive tool ecosystem: Vector CANoe/CANalyzer, dSPACE tools, and ETAS INCA are the standard tools used to validate and measure the correct behaviour of the systems described in this lesson. Familiarity with these tools alongside the conceptual knowledge dramatically accelerates debugging in real projects.

⚠️ Common Mistakes and How to Avoid Them

Assuming default configuration is correct: Automotive software tools ship with default configurations that are designed to compile and link, not to meet project-specific requirements. Every configuration parameter needs to be consciously set. 'It compiled' is not the same as 'it is correctly configured'.
Skipping documentation of configuration rationale: In a 3-year ECU project with team turnover, undocumented configuration choices become tribal knowledge that disappears when engineers leave. Document why a parameter is set to a specific value, not just what it is set to.
Testing only the happy path: Automotive ECUs must behave correctly under fault conditions, voltage variations, and communication errors. Always test the error handling paths as rigorously as the nominal operation. Many production escapes originate in untested error branches.
Version mismatches between teams: In a multi-team project, the BSW team, SWC team, and system integration team may use different versions of the same ARXML file. Version management of all ARXML files in a shared repository is mandatory, not optional.

📊 Industry Note

Engineers who master both the theoretical concepts and the practical toolchain skills covered in this course are among the most sought-after professionals in the automotive software industry. The combination of AUTOSAR standards knowledge, safety engineering understanding, and hands-on configuration experience commands premium salaries at OEMs and Tier-1 suppliers globally.