Modern SoCs (Renesas R-Car H3, NXP S32G) integrate Cortex-R cores for Classic CP and Cortex-A cores for Adaptive AP on the same die. The inter-domain IPC bridge uses a shared memory region with defined ownership per domain — no hypervisor required for data exchange.
Cortex-R Core 0 (AUTOSAR Classic) Cortex-A Core (AUTOSAR Adaptive)
┌─────────────────────────────────┐ ┌────────────────────────────────┐
│ AUTOSAR Classic BSW │ │ AUTOSAR Adaptive Middleware │
│ CAN Rx → COM signal buffer │ │ SOME/IP skeleton: SpeedSvc │
│ Gateway SWC: │ │ ara::com::EventSendHandler │
│ Com_ReceiveSignal(SPEED, &v) │ │ SpeedSvc_Skeleton::Send() │
│ Serialize → SOME/IP payload │ └────────────────┬───────────────┘
│ Write to shared SRAM region │ │ Reads shared SRAM
└────────────────┬────────────────┘ │ via IPC bridge
│ Writes to shared SRAM │
└──────────── Shared SRAM (0x40000000) ─────┘
(write: Classic owns; read: Adaptive)
Protected by hardware semaphore or spinlock| SoC Platform | Classic Cores | Adaptive Cores | IPC Mechanism |
|---|---|---|---|
| Renesas R-Car H3 | 2× Cortex-R7 | 4× Cortex-A57 | ICCOM shared memory + hardware semaphore |
| NXP S32G3 | 4× Cortex-M7 + 2× Cortex-R52 | 4× Cortex-A53 | MU (Message Unit) + shared DDR |
| STM32MP25 | 2× Cortex-M33 | 1× Cortex-A35 | OpenAMP RPMsg over shared SRAM |